<aside> <img src="/icons/user_gray.svg" alt="/icons/user_gray.svg" width="40px" /> Fresher in VLSI Design and Verification Engineering

An enthusiastic newcomer in the world of VLSI Design and Verification Engineering. With a solid foundation in Electronics and Communication Engineering, I am fascinated by the intricate art of Front-End semiconductor design and verification and Computer Architecture.

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VLSI DV ENGINEER

Contacts

◽ [email protected]

◽ Kannur, Kerala

◽ +91 83019 60200

Skills

• Verilog
• System Verilog
• Digital System Design
• Python
• Linux
• Git

Tools

• Xilinx Vivado
• Mathlab
• LT Spice
• DC Compiler

Contact Me

Work Experience

Summer Intern

CSA Department, IISc Bangalore

June 2023

• Worked on Hardware Accelerator for DNN training
• My work includes contributions to RTL design of Router network in Multi-NoC Architecture

Intern

Indian Institute of Technology, Goa

May 2022

• Guided by Prof. Sharad Sinha
• Worked on the implementation of RTL design of an Approximate Divider

Education

B Tech Electronics and Communication

CGPA 9.3

Cochin University of Science and Technology, Kochi, Kerala

2020 - 24

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Portfolio

Projects

<aside> 🤞 Some direct links

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GitHub - Nidhinchandran47/HDLbits-Solutions: The HDL Bits Solutions repository provides answers to the HDL Bits exercises, which are designed for practicing digital hardware design using Verilog HDL. Join us to learn, share, and master digital design!

GitHub - Nidhinchandran47/DV200: A go-to repository for exploring, learning, and mastering RTL design and verification.